Digitally-controlled oscillator

ABSTRACT

A digitally-controlled oscillator comprises an input for the supply of a digital input word, an adder, a stable local oscillator and a delay circuit, comprising a delay stage with a number of serially-connected coarse delay elements and a fine delay stage with a number of serially-connected fine delay elements. The coarse delay stage and the fine delay stage are embodied such that the maximum total delay and the minimum total delay differ by at most one period of the cycle signal. The delay produced by the number of fine delay elements corresponds to the delay of one coarse delay element. Each coarse delay element and each fine delay element comprise their own controllable selector.

FIELD OF INVENTION

The invention relates to a digitally controlled oscillator in accordancewith the precharacterizing part of the independent patent claim.

BACKGROUND

Sending audio and video data in real time requires the data rate at thetransmitter and receiver to match in order to avoid impairing thereproduction quality as a result of underflows or overflows inbuffer-stores for data (buffers). The receiver accordingly also needs toreceive clock information which defines the exact data rate at alltimes. This clock information may come from the transmitter itself orelse from an external clock reference, and in the latter case thetransmitter also needs to be synchronized to this external clockreference.

In both cases, clock information needs to be distributed, however. Inthis context, the transmission is frequently not ideal, i.e. the clockis overlaid with jitter during distribution. For this reason, clockrecovery is frequently used, the task of which is to suppress or reducethis jitter by means of filtering (and possibly also to multiply theclock frequency).

Clock recovery with jitter suppression is normally implemented by aphase trimming circuit PLL (phase-locked loop). The clock generator usedfor the PLL is frequently voltage controlled oscillators VCO. However,such VCOs have, as analog circuits, the drawback that they can beintegrated on an application-specific integrated circuit ASIC only incomplex fashion.

Digitally controlled oscillators DCO are far superior to an analog VCOnot only in respect of their integratability in an ASIC but also inrespect of their power and area requirements. Most DCOs are based on aDLL (Delay-Locked Loop) or on a ring oscillator. Although ringoscillators may be used for jitter suppression (jitter filtering), thelow frequency resolution and the high susceptibility to natural jitterlimit the range of application of ring oscillators. Althoughconventional DLL-based implementations of DCOs can multiply thefrequency of the input signal, they provide no jitter filtering, sincethere is no genuine frequency synthesis involved.

A PLL with a DLL-based solution for a DCO has already been described inUS-A-2002/0008557. The DCO is clocked by a stable oscillator. Inaddition, the DCO comprises an adder which generates a desired outputfrequency. An input word is repeatedly added to a start value for theadder, so that the adder fills or overflows cyclically. Once the adderhas filled or overflowed, a rising edge of the output signal isgenerated upon the next rising edge of the input clock (clock from thestable oscillator). If generation of the rising edge of the outputsignal produces a “remnant term” on the adder (that is to say if theinput word added to the counter reading of the adder was larger than theremaining capacity of the adder), this remnant term (which is that partof the input word which exceeds the capacity of the adder) is written toa register and represents the timing error in the output signal. Theremnant term is used to actuate a multistage delay circuit (coarsedelay, fine delay). The delay circuit has a plurality of delay stages(coarse delay stage, fine delay stage), each delay stage being providedwith individual discrete taps downstream of each delay element. In thiscase the remnant term controls which of the taps in the delay stage isrespectively tapped off so that the output signal (which, of course, hasa timing error which is represented by the remnant term) can be delayedsuch that the timing error in the output signal is compensated for whenthe correspondingly delayed output signal then has the correct phaseagain.

To select the respectively suitable tap, the delay stage contains amultiplexer (selector) whose inputs are connected to the individual tapsdownstream of the respective delay elements (specifically a respectiveinput on the multiplexer is connected to a tap downstream of a delayelement), so that the remnant term can actuate the multiplexer such thatthe corresponding tap is selected for which the output signal is delayedsuch that the timing error is compensated for.

This is done by virtue of a coarse delay stage taking the coarse delayelements it contains as a basis for first of all coarsely delaying theoutput signal. The coarse delay stage delays the output signal asclosely as possible to the delay which is required in order tocompensate for the timing error, as is possible on the basis of thedelay by the individual coarse delay elements (at most just as far asthe required delay; if this is not exactly possible on the basis of thedelay by the individual coarse delay elements, then as far as thatcoarse delay which is just below the delay which is required for thecompensation). The signal delayed by the coarse delay stage is thendelayed further in at least one fine delay stage (or else in a pluralityof fine delay stages) until the delay which is necessary in order tocompensate for the timing error is reached (or as close to this as isactually possible on the basis of the delay by the individual fine delayelements). The fine delay stage is designed such that passing throughall of the fine delay elements (maximum delay by the fine delay stage)brings about a delay which corresponds to exactly one coarse delayelement.

The difference between the maximum and minimum delays by the entiredelay circuit (coarse delay stage and fine delay stages) is exactly oneperiod of the input clock (clock from the stable oscillator).

As already mentioned, the inputs of the multiplexer need to be connectedto the many individual taps on a delay stage of this type, which causessignificant difficulties for the implementation of such a delay stage inan integrated circuit (e.g. on silicon), because each tap downstream ofa delay element needs to be connected to the input of the multiplexer bya connection of equal length (or in better terms: of equal shortness) sothat no relevant propagation time differences arise on the path from thetaps downstream of the individual delay elements to the inputs of themultiplexer (otherwise the accuracy of the delay would be impaired noless than considerably, if the operability were not actually seriouslycalled into question).

In the case of the coarse delay stage described in US-A-2002/0008557,these alone are 64 taps which need to be connected to the inputs of themultiplexer. However, beyond the 64 taps which are used, the individualdelay stages normally also contain a significantly larger number ofdelay elements which are not always all used, however, but whose tapsstill need to be connected to the inputs of the multiplexer, because,depending on the application, it is, of course, not known beforehand howmany delay elements are actually needed for a particular application.Hence, taking into account the stipulation that no relevant propagationtime differences must arise, the difficulties in implementing a delaystage of this type in silicon become immediately clear uponconsideration of the propagation time for the signals between respectivetaps and the associated inputs of the multiplexer.

SUMMARY

It is therefore an object of the invention to propose a digitallycontrolled oscillator of the type mentioned above but in which theimplementation of the delay circuit in an integrated circuit (e.g. onsilicon) is much simpler.

This object is achieved by the inventive digitally controlled oscillatoras characterized by the features of independent patent claim 1.Advantageous exemplary embodiments of a digitally controlled oscillatorof this type can be found in the features of the dependent patentclaims.

In particular, each coarse delay element and each fine delay elementcomprises a dedicated actuatable selector. This has the advantage that alarge number of signals distributed over individual taps do not all haveto be routed to a selector which then selects the respectivetap—corresponding to the required delay. This allows simplerimplementation in an integrated circuit, because a multiplicity of taps,namely downstream of every single delay element, is not required and isalso not present.

In one advantageous exemplary embodiment of the inventive digitallycontrolled oscillator, the coarse delay element comprises a delayelement and the selector, with one input on the selector in therespective coarse delay element being connected to the output of thedelay element of the same coarse delay element and a further input onthe selector being connected to the output of the selector in the coarsedelay element connected immediately downstream. That is to say that eachselector requires, in principle, only two signal supplies, namely theoutput signal from its own delay element and the output signal from theselector in the delay element connected immediately downstream. Thismeans that implementation in silicon is a particularly simple matter,and that separate taps do not exist downstream of the individual delayelements and are also not needed.

In a further exemplary embodiment of the inventive digitally controlledoscillator, the fine delay element has a common input and at least twodrivers connected to the common input. A capacitive load is provided atthe output of one of the two drivers (in the case of exactly twodrivers). One input on the selector is connected to the output of thedriver without the capacitive load and a further input on the selectoris connected to the output of the driver with the capacitive load. Theoutput of the selector in the respective fine delay element is connectedto the common input of the fine delay element connected immediatelydownstream. Charging the capacitive load causes the signal not to beapplied until at a later time, because the capacitive load needs to becharged first. Since both the output signal from the driver without acapacitive load and the output signal from the driver with a capacitiveload are applied to the inputs of the selector, the selector can easilyselect whether or not the delay brought about by the capacitive load isactivated in the case of the respective delay element. Another advantageof this is that only drivers of the same type can be used to achieve afine delay which is shorter than the fine delay in an individual driver,because the propagation times of the signal through the two paths differby less than the propagation time through a single driver.

In a further advantageous exemplary embodiment of the inventivedigitally controlled oscillator, the fine delay element comprises aplurality of drivers whose inputs are connected to one another to form acommon input and whose outputs are connected to one another to form acommon output. In this case, the selector is designed such that theindividual drivers may be activated or deactivated. The common output isconnected to the common input of the fine delay element connectedimmediately downstream. In this case, the selector is in a form suchthat the individual drivers may be activated (“enabling”) or not. Theindividual drivers each have an input capacitance, regardless of whetheror not the respective driver has been activated. Hence, the more driversthere are activated in a preceding fine delay element, the less time isrequired before the input capacitances of the subsequent fine delayelement are charged, and the faster the output signal is then applied tothe common output. In this way, it is thus a very simple matter to setthe delay time of the individual delay elements.

In addition, the invention also relates to a digital phase trimmingcircuit, having an input clock signal, a phase comparator, a filter anda digitally controlled oscillator, and having a feedback path whichfeeds back an output signal generated by the digitally controlledoscillator to the phase comparator, possibly with frequency division. Inthis case, the digitally controlled oscillator is designed as describedabove.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantageous refinements of the inventive digitally controlledoscillator can be found in the description below of exemplaryembodiments with reference to the drawing, in which:

FIG. 1 shows a block diagram of an exemplary embodiment of a fewfundamental elements of an inventive digitally controlled oscillator(DCO);

FIG. 2 shows an illustration of a stable input clock of the DCO and ofan input clock generated by the DCO;

FIG. 3 shows a period of the stable input clock with possible divisionof this period into time slots which correspond to the delays by thecoarse delay elements and to the delays by the fine delay elements;

FIG. 4 shows a block diagram to explain the calibration operation whencalibrating the coarse delay stage;

FIG. 5 shows a block diagram to explain the calibration operation whencalibrating the fine delay stage;

FIG. 6 shows an exemplary embodiment of a coarse delay stage withindividual coarse delay elements;

FIG. 7 shows a first exemplary embodiment of a fine delay stage withindividual fine delay elements;

FIG. 8 shows a second exemplary embodiment of a fine delay stage withindividual fine delay elements; and

FIG. 9 shows a block diagram of a phase trimming circuit (PLL) with aninventive DCO.

DETAILED DESCRIPTION

The block diagram in FIG. 1 shows a few fundamental elements of anexemplary embodiment of an inventive digitally controlled oscillator 1.The latter comprises an adder 10 for summing digital input words 100which are supplied to the adder 10. These digital input words arerepresentative of the respective frequency generated at the output ofthe digitally controlled oscillator 1. The digital input words 100 aresummed in the adder 10, which actuates the delay stages, in theexemplary embodiment shown here a coarse delay stage 11 and a fine delaystage 12, in a manner which will be explained in more detail. The coarsedelay stage 11 comprises a plurality of coarse delay elements 110, andthe fine delay stage 12 comprises a plurality of fine delay elements120, only a very limited number of coarse delay elements 110 and finedelay elements 120 being shown in each case in FIG. 1 for reasons ofbetter clarity.

FIG. 2 shows the input clock from a stable local oscillator at theconstant frequency f₀, the stable local oscillator not being shown inFIG. 1; such stable local oscillators (e.g. highly stable crystaloscillators) are sufficiently well known. The output frequency f of theoutput clock generated by the digitally controlled oscillator differsfrom the frequency f₀ of the input clock generated by the stable localoscillator. In this case, the digitally controlled oscillator thus takesthe input words as a basis for generating a frequency f which differsfrom the frequency f₀ of the input clock.

This can easily be seen in FIG. 2 from the fact that the phasedifference Δφ between the respective rising edge of the input clock atthe frequency f₀ and the rising edge of the output clock at thefrequency f (which is likewise constant in this case) always increasesby a constant amount. A constant increase in the phase difference Δφmeans nothing other than a constant frequency difference, however.

In principle, of course, what is involved is the use of the digitallycontrolled oscillator to replace a clock which may be subject to jitterwith a low-jitter clock (of the same frequency and phase) which isgenerated using the (jitter-free) input clock from the stable localoscillator (or by a clock at a multiple or a fraction of this clockfrequency), with the delay stages being used too. The way in which thissimulation of the input clock using a (jitter-free) input clock from thestable local oscillator takes place on the basis of the fundamentalprinciple is already revealed by US-A-2002/0008557, which was mentionedat the outset.

To this end, however, it is necessary to know how many coarse delayelements 110 and how many fine delay elements 120 are required and howmany fine delay elements 120 are needed in order to effect the maximumadmissible delay when all of the coarse delay elements 110 are activated(the difference between the maximum and minimum delays must be no morethan one period duration of the stable input clock).

FIG. 3 shows one period of the input clock at the frequency f₀ and ofthe corresponding period duration T₀ (where: T₀=1/f₀), with possibledivision of the period duration T₀ into time slots T_(c) and T_(f) whichcorrespond to the delays by the coarse delay elements 110 (FIG. 1) andthe delays of the fine delay elements 120 (FIG. 1).

FIG. 3 shows that the required number of coarse delay elements 110 isdetermined such that the sum of the delays T_(c) which is effected bythis number of coarse delay elements 110 is just smaller than one periodduration T₀ of the input clock. The required number of fine delayelements 120, on the other hand, is determined such that the sum of thedelays T_(f) which is effected by this number of fine delay elements 120is just equivalent to the delay T_(c) by a coarse delay element 110. Inaddition, it is also necessary to determine the required number of finedelay elements 120 which is necessary in order to achieve a total delaywhich is exactly equivalent to one period duration T₀ of the input clock(or is just shorter), that is to say the difference between the periodduration T₀ of the input clock and the delay which is effected by thepreviously determined number of coarse delay elements. This differencelikewise corresponds to a number of fine delay elements which is smallerthan the total required number of fine delay elements, however.Nevertheless, it is also necessary to determine this number of finedelay elements, since the difference between the maximum and minimumtotal delay which are effected by the two delay stages together needs tobe shorter than one period duration T₀ of the input clock.

FIG. 4 shows a block diagram of how the calibration operation takesplace when calibrating the coarse delay stage 11, that is to say how thenumber of coarse delay elements 110 is determined which together effecta coarse delay which is just below a period duration T₀ of the inputclock from the stable local oscillator at the frequency f₀. To this end,two paths have a stable input clock at the frequency f₀/4 (periodduration 4T₀) applied to them as a signal. This clock signal at thefrequency f₀/4 may be obtained, by way of example, through “clockgating” from the clock signal at the frequency f₀ in the stable localoscillator (frequency division). This lower frequency may becomenecessary because the “offset delays” in the delay stages 11, 12 may betoo great for the clock signal at the frequency f₀ of the stable localoscillator to be able to be used directly, which may be due to thechoice of a particular semiconductor for the integrated circuit, forexample. When very fast semiconductors (or a lower frequency for thestable local oscillator) are chosen, the frequency f₀ of the stablelocal oscillator may also be used directly.

The first path contains a coarse delay stage 11 which is to becalibrated, which comprises a number of coarse delay elements 110. Thiscoarse delay stage 11 is followed by a fine delay stage 12 which ispassed through in idle mode (no fine delay element activated) and whichis basically passed through by the signal only because it may have an“offset” delay without even just a single fine delay element 120 havingbeen activated.

In the second path, the signal first passes through a delay element 13which delays the signal by precisely the duration T₀, and hence thesignal in the second path is then delayed by one quarter period withrespect to the signal in the first path. The signal then passes througha coarse delay stage 11 which is operated in idle mode. The subsequentfine delay stage 12 in the second path is also operated in idle mode (nofine delay element activated).

The output signals from the fine delay stages 12 in the two paths is nowsupplied to a phase comparator 14 which compares the phases of the twosignals to one another. Since the signal which has passed through thesecond path is behind the signal which has passed through the first pathby one quarter of the period duration (namely by T₀, note: periodduration of the signal is 4T₀ in this case), without taking into accountthe coarse delay stage 11 in the first path, the number of coarse delayelements 110 in the coarse delay stage 11 which is to be calibrated inthe first path now needs to be ascertained such that the signal, uponpassing through the number of coarse delay elements 110 ascertained inthis manner, is almost in phase with the signal which has passed throughthe second path.

To this end, a coarse delay element 110 in the first path is firstactivated and the phase comparator 14 respectively compares the phasesof the output signals from the fine delay stages 12 in the two paths. Ifthe phase difference corresponds to a delay which is greater than thedelay by a coarse delay element 110, then a controller 15 activates afurther coarse delay element 11C. Next, the signal (stable input clock)passes through the two paths again and the phase comparator 14 performsa fresh comparison between the phases. This is repeated until the phasedifference on the phase comparator 14 is just short of corresponding toa delay through a coarse delay element 110. The required number ofcoarse delay elements 110 has thus been ascertained.

The way in which the fine delay stage 12 is calibrated can be seen fromFIG. 5. It is thus necessary to ascertain the number of fine delayelements 120 in a fine delay stage 12 which together effect a delaycorresponding to the delay by a single coarse delay element 110 in thecoarse delay stage 11. To this end, two paths have a stable input clock,e.g. the clock from the stable local oscillator (frequency f₀, periodduration T₀), applied to them as a signal.

In the second path, the signal passes through a coarse delay stage 11having a single activated delay element 110 and then passes through afine delay stage 12 in idle mode (no fine delay element 120 activated).

In the first path, the signal passes through a coarse delay stage 11 inidle mode (no coarse delay element 110 activated) and then passesthrough a fine delay stage 12 which is to be calibrated. The outputsignals from the fine delay stages 12 in the two paths are supplied tothe phase comparator 14, which compares the phases of the two signalswith one another.

Initially disregarding the delay effected by the fine delay elements 120in the first path, the output signal from the second path is thusdelayed compared to the signal in the first path by the coarse delayeffected by the single activated coarse delay element 110. This delaycorresponds to a phase difference which is applied to the phasecomparator 14. Next, the signal (stable input clock) passes through thetwo paths again and the phase comparator compares the phases again. Thisis repeated until the phase difference on the phase comparator 14 isjust short of corresponding to a delay by a coarse delay element 110.The required number of coarse delay elements 110 has thus beenascertained.

If this phase difference corresponds to a delay which is still greaterthan the delay by a fine delay element 120, the controller 15 activatesa further fine delay element 120 in the fine delay stage 12 in the firstpath. Next, the signal (stable input clock) passes through the two pathsagain and the phase comparator compares the phases again. This isrepeated until the phase difference on the phase comparator 14 is zero(or until the phase difference corresponds to a delay which is shorterthan the delay by a fine delay element 120).

The number of required fine delay elements 120 which correspond to acoarse delay element 110 has thus been ascertained.

Finally, it is also necessary to ascertain how many fine delay elements120 are required in addition to the ascertained number of coarse delayelements 110 in order to bring about a delay which corresponds preciselyto the period duration T₀ of the input clock. This is basically done inthe same manner as when ascertaining the required number of coarse delayelements 110 (that is to say frequency f₀/4, period duration 4T₀), butwith the number of coarse delay elements 110 having been prescribed(since it is that number of coarse delay elements which effect a delaywhich is shorter than the period duration T₀ of the clock from thestable local oscillator by less than the delay of a single coarse delayelement). Then, only the number of fine delay elements 120 is determinedwhich, together with the coarse delay elements 110, effects a delaywhich corresponds to precisely one period duration (or which effects adelay which is shorter than the period duration of the input clock byless than the delay of a single fine delay element).

These three bits of information (number of coarse delay elementsrequired maximum, number of fine delay elements required maximum, numberof fine delay elements required to achieve the maximum delay time)concludes the calibration.

The respective total delay (delay by the coarse delay stage 11 and bythe fine delay stage 12) is now always proportional to the accumulatedcounter reading for the adder 10. If a counter reading is reached whichcorresponds to the maximum possible delay, ‘gating’ takes place (thenext rising edge of the input clock is ignored), the counter is resetagain and that portion of the last input word which exceeds the maximumcounter reading is used to actuate the coarse delay stage 11 and thefine delay stage 12. Next, the digital input words are added again, andthe accumulated counter reading corresponds to the respective totaldelay again, until the counter overflows again, and so on.

FIG. 6 shows a preferred exemplary embodiment of a coarse delay stage 11with individual coarse delay elements 110. It can be seen that eachcoarse delay element 110 comprises a delay element 110 b and a selector110 c. The input of the selector 110 c in the respective coarse delayelement 110 is connected to the output of the same coarse delay element110. A further input on the selector 110 c is connected to the output ofthe selector in the delay element 110 connected immediately downstream.

Looking at the first delay element 110 (in FIG. 6 the one arranged atthe far left), for example, the signal applied to the input 110 a thusfirst passes through the delay element 110 b and is then already appliedto an input of the selector 110 c in the same delay element 110. If theselector 110 c in the first delay element 110 were to be actuated suchthat the input of the selector 110 c to which the signal delayed by thedelay element 110 b is applied switches through to the output 110d—which in this case corresponds to the output 110 e of the coarse delaystage 11 at the same time, then the output signal from the coarse delaystage 11 would be delayed all in all only by the delay effected by thedelay element 110 a and the selector 110 c. The delay elements 110connected downstream would accordingly not be activated.

The downstream delay elements 110 are designed in the same way as thefirst delay element 110, with just the last delay element 110 (arrangedat the far right of FIG. 6) having the same signal applied to the twoinputs of the selector 110 c, said signal being applied to the inputs ofthe selector 110 c in this last delay element 110 following a delaywhich corresponds to the number of delay elements 110.

The signal which is respectively connected through the output 110 d of aselector is stipulated using a selection connection 110 f on therespective selector 110 c. The inputs of each selector 110 c thus justhave two signals applied to them, the signal routing beingcorrespondingly simple and being very easy to implement in silicon.

FIG. 7 shows a first exemplary embodiment of a fine delay stage 12. Thisexemplary embodiment of the fine delay stage 12 comprises a plurality offine delay elements 120 which each have an input 120 a and an output 120b. The output 120 b of a preceding fine delay element 120 (e.g. the finedelay element 120 on the far left) is respectively connected to theinput 120 a of the subsequent fine delay element 120 (the second finedelay element 120 from the left). The output 120 b of the last finedelay element 120 is simultaneously the output of the fine delay stage12.

Each fine delay element 120 comprises two paths, a first path with a“buffer” 120 c, whose output is connected to an input on a selector 120f, and a second path, which contains a further buffer 120 d whose outputis firstly connected to a further input on the selector 120 f and whichsecondly has a further buffer 120 e appended to it. The input of thetime delay element branches into the two paths (in principle, it wouldalso be possible to have a plurality of such paths, but the exemplaryembodiment shown has exactly two).

When passing through the second path (containing the buffers 120 d and120 e), the signal requires more time before it reaches the outlet ofthe selector 120 f, because the second buffer 120 e can be considered tobe a capacitive load which first needs to be charged before the signalis then applied to the input of the selector and can be switched throughto its output 120 b. The passage through the second path thuscorresponds to a time delay, because the signal cannot be applied to theinput of the selector and hence also to the latter's output until at alater time. The selector comprises a selection connection 120 g whichcan be used to select whether the signal in the first path or the signalin the second path is switched through to the output 120 b. It is thuspossible to set separately on each individual fine delay element 120whether the signal which has passed through the first path or the signalwhich has passed through the second path is set. This is equivalent tonothing other than setting the fine delay which is set in thecalibration already outlined in detail further above.

FIG. 8 shows a second exemplary embodiment of the fine delay stage 12with a plurality of fine delay elements 120. In this exemplaryembodiment of the fine delay stage 12, each fine delay element 120comprises an input 120 h and an output of 120 i. The output 120 i of apreceding fine delay element 120 (e.g. the fine delay element 120 on thefar left) is respectively connected to the input 120 h of the subsequentfine delay element 120 (the second fine delay element 120 from theleft). The output 120 i of the last fine delay element 120 issimultaneously the output of the fine delay stage 12.

Each fine delay element 120 comprises a plurality of paths whichrespectively contain a “tristate buffer” 120 j. In the exemplaryembodiment shown, there are a total of four parallel paths containing arespective tristate buffer 120 j. In this arrangement, the input 120 hof the fine delay element 120 branches into the four paths which containthe tristate buffers 120 j.

In this case, the selector is designed such that each tristate buffer120 j can be activated or deactivated using a dedicated selectionconnection 120 k. The tristate buffers have an input capacitanceregardless of whether or not they have been activated. The more buffersare activated within a fine delay element 120, the less time it takesbefore the input capacitance in the subsequent delay element has beencharged, and the faster the signal supplied to the output of therespective fine delay element 120. In this case too, the fine delaystage is calibrated in the manner already described further above.

FIG. 9 shows a block diagram showing fundamental elements of a phasetrimming circuit PLL (Phase-Locked Loop) which comprises a digitallycontrolled oscillator as described above. The phase trimming circuit PLLcomprises a phase comparator 2, a filter 3 for filtering outhigh-frequency jitter, a digitally controlled oscillator 1 designed asdescribed above, and a frequency divider 4 in the feedback path.

The input (clock) signal affected by jitter (which incidentally is notto be confused with the input clock signal generated by the stable localoscillator in the DCO) needs to be stimulated with the correct frequencyand phase by a low-jitter output clock signal. This is done using thedigitally controlled oscillator which has been described above, with thephase comparator 2 checking for the correct phase.

Specific embodiments of a digitally controlled oscillator according tothe present invention have been described for the purpose ofillustrating the manner in which the invention may be made and used. Itshould be understood that implementation of other variations andmodifications of the invention and its various aspects will be apparentto those skilled in the art, and that the invention is not limited bythe specific embodiments described. It is therefore contemplated tocover by the present invention any and all modifications, variations, orequivalents that fall within the true spirit and scope of the basicunderlying principles disclosed and claimed herein.

1. A digitally controlled oscillator for generating a correct-phaseoutput signal at a desired frequency, having an input for supplying adigital input word, an adder for summing the digital input words, astable local oscillator for supplying a clock signal at a constantfrequency, and a delay circuit which comprises a coarse delay stagehaving a plurality of series-connected coarse delay elements and a finedelay stage having a plurality of series-connected fine delay elements,where the coarse delay stage and the fine delay stage are designed suchthat the total delay of the coarse delay stage and the fine delay stageis proportioned such that the maximum total delay and the minimum totaldelay of the delay circuit differ by no more than one period of theclock signal, and where the plurality of fine delay elements correspondsto the delay by one coarse delay element, wherein each coarse delayelement and each fine delay element comprises a dedicated actuatableselector.
 2. The digitally controlled oscillator as claimed in claim 1,in which the coarse delay element comprises a delay element and theselector, with one input on the selector in the respective coarse delayelement being connected to the output of the delay element of the samecoarse delay element and a further input on the selector being connectedto the output of the selector in the coarse delay element connectedimmediately downstream.
 3. The digitally controlled oscillator asclaimed in claim 1, wherein the fine delay element has a common inputand at least two drivers connected to the common input, with acapacitive load being provided at the output of one of the two drivers,which oscillator also has one input on the selector connected to theoutput of the driver without the capacitive load and a further input onthe selector connected to the output of the driver with a capacitiveload, and which oscillator has the output of the selector in therespective fine delay element connected to the common input of the finedelay element connected immediately downstream.
 4. The digitallycontrolled oscillator as claimed in claim 1, wherein the fine delayelement comprises a plurality of drivers whose inputs are connected toone another to form a common input and whose outputs are connected toone another to form a common output, in which also the selector isdesigned such that the individual drivers may be activated ordeactivated, and in which the common output is connected to the commoninput of the fine delay element connected immediately downstream.
 5. Adigital phase trimming circuit (PLL), having an input clock signal,having a phase comparator, a filter, a digitally controlled oscillator,and a feedback path which feeds back an output signal generated by thedigitally controlled oscillator to the phase comparator, includingfrequency multiplication and/or frequency division, wherein thedigitally controlled oscillator is designed in accordance with claim 1.